1. Field of the Invention
This invention relates to a gate driving circuit for driving an insulated gate switching element.
2. Description of the Related Art
Recently, insulated gate switching elements (sometimes known as power metal oxide semiconductors, or, hereinafter, power MOSs) such as insulated gate bipolar transistors (IGBTs) and power MOS field effect transistors (power MOSFETs) have been widely used in power conversion devices, and accordingly the application of the power MOSs to hybrid vehicles, electric vehicles, and so on has recently attracted attention.
FIG. 8 is a circuit diagram of a gate driving circuit for driving a power MOS according to the related art. This gate driving circuit 50 includes an inverter circuit 51 having a p-channel MOSFET QP1 and an n-channel MOSFET QN1 connected in series (having the drains respectively connected to each other). A high potential side power supply terminal Vcc of the gate driving circuit 50 is connected to a source of a p-channel MOSFET QP1, and a low potential side power supply terminal GND is connected to a source of an n-channel MOSFET QN1.
An input terminal Vin of the inverter circuit 51 is connected to a gate of each of the p-channel MOSFET QP1 and the n-channel MOSFET QN1. A connection point of the p-channel MOSFET QP1 and the n-channel MOSFET QN1 is connected to one end of a gate resistor R1, and the other end of the gate resistor R1 is connected to an output terminal Vout. An anode of a diode D1 is connected to the low potential side terminal GND, and a cathode of the diode D1 is connected to the output terminal Vout. The diode D1 is a protection diode for preventing an excessive voltage from being applied to the output terminal Vout. Further, a voltage Vd1 is a voltage between the connection point of the p-channel MOSFET QP1 and the n-channel MOSFET QN1 and the low potential side terminal GND, and is the same as a drain-source voltage Vds1 of the n-channel MOSFET QN1.
FIG. 9 is diagram of a main circuit using a power MOSFET as a power MOS. Here, a main circuit 60 used for an electric vehicle or the like will be described. A power supply of the main circuit 60 is different from the power supply of the gate driving circuit 50, and a voltage of a high potential side power supply terminal Vcco of the main circuit 60 is higher than that of the high potential side power supply terminal Vcc of the gate driving circuit 50. In the case of an electric vehicle, a load is an electric motor, and an equivalent circuit of the electric motor becomes a circuit including a resistor R2 and an inductor L1 connected in series. Also, the power MOSFET is an re-channel type, and herein is denoted by QN4. In the power MOSFET QN4, a gate-drain capacitance is denoted by Cgd, a gate-source capacitance is denoted by Cgs, and a drain-source capacitance is denoted by Cds. A voltage between a connection point of the inductor L1 and the power MOSFET QN4 and the low potential side terminal GND is denoted by Vd3, and is the same as a drain-source voltage Vds4 of the power MOSFET QN4.
Next, a configuration of the main circuit 60 will be described. The high potential side power supply terminal Vcco of the main circuit 60 is connected to the resistor R2, a drain of the power MOSFET QN4 is connected to the inductor L1, and a source of the power MOSFET QN4 is connected to the low potential side power supply terminal GND. A gate of the power MOSFET QN4 is connected to a gate terminal Vg. The gate-drain capacitance Cgd is provided between the gate and drain of the power MOSFET QN4, the gate-source capacitance Cgs is provided between the gate and source of the power MOSFET QN4, and the drain-source capacitance Cds is provided between the drain and source of the power MOSFET QN4. A gate capacitance Cg of the power MOSFET QN4 is the same as the sum of the gate-source capacitance Cgs and the gate-drain capacitance Cgd.
FIG. 10 is a diagram of a circuit used for a simulation of a case where the output terminal Vout of FIG. 8 is connected to the gate terminal Vg of the FIG. 9. If the n-channel MOSFET QN1 constituting the inverter circuit 51 of the gate driving circuit 50 is turned on, and the p-channel MOSFET QP1 is turned off, the power MOSFET QN4 of the main circuit 60 is turned off.
FIG. 11 is a diagram illustrating the individual waveforms of the voltage Vd1 which is the same as the drain-source voltage Vds1 of the n-channel MOSFET QN1, a current Id1 flowing in the n-channel MOSFET QN1, a voltage of the input terminal Vin, and a voltage Vd3 which is the same as the drain-source voltage Vds4 of the power MOSFET QN4, when the n-channel MOSFET QN1 is in the ON state in FIG. 10. The voltage Vd1 and the voltage Vd3 are voltages relative to the potential of the low potential side terminal GND.
FIG. 12 is a diagram illustrating the waveforms of the voltage Vd1 and a drain current Id1 flowing in the n-channel MOSFET QN1, when the n-channel MOSFET QN1 is in the ON state in FIG. 10.
If a high-potential signal is input to the input terminal Vin of FIG. 10, the n-channel MOSFET QN1 constituting the gate driving circuit 50 changes to the ON state, and the potential of the output terminal Vout becomes a low level. Therefore, the power MOSFET QN4 having the gate connected to the output terminal Vout is turned off.
The voltage Vd1, which is the same as the drain-source voltage Vds1 of the n-channel MOSFET QN1, gradually decreases from the voltage of the high potential side terminal Vcc. This is because the charge accumulated in the gate capacitance Cg (=Cgs+Csd) of the power MOSFET QN4 becomes a drain current Id1 of the n-channel MOSFET QN1 to be discharged to the low potential side terminal GND. As shown in a portion A, in a state in which the voltage Vd1 (which is the same as the drain-source voltage Vds1 of the n-channel MOSFET QN1) is high, a large amount of drain current Id1 flows. Therefore, hot-carriers are generated in the n-channel MOSFET QN1, which deteriorates the element characteristics of the n-channel MOSFET QN1. Examples of element characteristic deterioration include threshold voltage shift, a decrease in drain current, and so on.
As shown in FIG. 9, in a case where the load is a motor (shown by a reference symbol “L1” in FIG. 9), a surge voltage Vs is applied between the drain and source of the power MOSFET QN4 by an induced electromotive force of the motor so that the drain-source voltage Vds4 of the power MOSFET QN4 increases sharply.
The surge voltage Vs is represented as a product of the inductance L of the inductor L1 and a current reduction rate di/dt when the power MOSFET QN4 is turned off. In other words, an equation of Vs=L×di/dt is established. The voltage vd3 relative to the low potential side terminal GND (which is the same as the drain-source voltage Vds4 of the power MOSFET QN4) becomes a voltage obtained by superimposing the surge voltage Vs on the voltage of the high potential side terminal Vcco.
Since the gate and drain of the power MOSFET QN4 are linked to each other through the gate-drain capacitance Cgd of the power MOSFET QN4, the surge voltage Vs influences the gate of the power MOSFET QN4 so that the potential of the gate terminal Vg of the power MOSFET QN4 increases.
However, at the positions where the voltage Vd1 is increased by the influence of the drain-source voltage Vds4 (=Vd3) of the power MOSFET QN4, the voltage Vd1 is decreasing as shown by a reference symbol “B” in FIG. 12. In simulations, the degree of the increase is small.
Moreover, if the inductance L of the inductor L1 is large, the falling of the voltage Vd1 is plateaus before it falls as shown by a dotted line C, resulting in the drain-source voltage Vds1 (=Vd1) of the n-channel MOSFET QN1 to be maintained at a high level. Therefore, the inductance L of the inductor L1 increases, an amount of hot-carriers generated in the n-channel MOSFET QN1 also increases.
As described above, since the drain current Id1 flows in the n-channel MOSFET QN1 in the state in which the drain-source voltage Vds1 (=Vd1) of the n-channel MOSFET QN1 is high, the hot-carriers are generated in the n-channel MOSFET QN1, and causes element characteristic deterioration. The amount of hot-carriers becomes larger as the drain-source voltage Vds1 of the n-channel MOSFET QN1 increases, is proportional to the drain current Id1, and is proportional to the sixth power of the voltage Vd1.
Therefore, when the power MOSFET QN4 is turned off, a lot of hot-carriers are generated in the n-channel MOSFET QN1, so as to cause element deterioration.
Further, when the p-channel MOSFET QP1 of FIG. 8 is turned on so as to turn on the power MOSFET QN4, similarly, hot-carriers are generated in the p-channel MOSFET QP1, so as to cause element deterioration.
The hot-carriers are carriers (electrons and holes) that come to get energy due to a high electric field. When the hot-carriers enter a gate insulating film or the like of a MOS device, in the MOS device, the threshold voltage is shifted or the drain current decreases. That is, the hot-carriers cause element characteristic deterioration.
Next, a method of lowering the surge voltage Vs generated at the time of turning-off will be described.
For example, Japanese Patent Application Laid Open (JP-A) No. 7-99429 discloses a method of suppressing generation of a surge voltage Vs by actively increasing a gate voltage of a power MOS to allow a surge current to flow to the power MOS when the surge voltage Vs is generated.
Further, IEEE Journal of Solid-State Circuit, vol. SC-21, February 1986, pp. 187-192 discloses a circuit (NOEMI circuit) using a technology called normally-on enhancement MOSFET insertion (NOEMI). This circuit is a circuit including a MOSEFT, which is a normally-on enhancement MOSFET (NOEM) that is normally in an ON state, so as to suppress an amount of hot-carriers generated in a MOSFET connected in series with the NOEM.
The method of the JP-A No. 7-99429 is effective in protecting the power MOS. However, since the drain-source voltage Vds1 (=Vd1) of the n-channel MOSFET QN1 constituting the gate driving circuit 50 is high, hot-carrier generation in the n-channel MOSFET QN1 cannot be prevented by the method of JP-A No. 7-99429.
Also, IEEE Journal of Solid-State Circuit, vol. SC-21, February 1986, pp. 187-192 discloses that an NOEMI circuit is used in an integrated circuit such as an SRAM or a DRAM so as to suppress the generation of hot-carriers. However, it does not disclose that an NOEMI circuit is used in a gate driving circuit for driving a power MOS so as to suppress the amount of hot-carriers generated in a MOSFET constituting the gate driving circuit.